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author | Gwenolé Beauchesne <gbeauchesne@mandriva.org> | 2003-06-04 18:44:09 +0000 |
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committer | Gwenolé Beauchesne <gbeauchesne@mandriva.org> | 2003-06-04 18:44:09 +0000 |
commit | 4cd6a4a5d7e49d54d53dcf4a6f3393d50bd88e8b (patch) | |
tree | acd4001a266a8713495af7f1b2102b61e67113b0 /mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h | |
parent | 71b111ec6c4671667a19c6fbe0023d33422535d7 (diff) | |
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Import dietlibc 0.22 + other fixes for AMD64
Diffstat (limited to 'mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h')
-rw-r--r-- | mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h b/mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h new file mode 100644 index 000000000..98e4e09ce --- /dev/null +++ b/mdk-stage1/dietlibc/include/asm/sparc-sigcontext.h @@ -0,0 +1,50 @@ + +#define __SUNOS_MAXWIN 31 + +/* This is what SunOS does, so shall I. */ +struct sigcontext { + int sigc_onstack; /* state to restore */ + int sigc_mask; /* sigmask to restore */ + int sigc_sp; /* stack pointer */ + int sigc_pc; /* program counter */ + int sigc_npc; /* next program counter */ + int sigc_psr; /* for condition codes etc */ + int sigc_g1; /* User uses these two registers */ + int sigc_o0; /* within the trampoline code. */ + + /* Now comes information regarding the users window set + * at the time of the signal. + */ + int sigc_oswins; /* outstanding windows */ + + /* stack ptrs for each regwin buf */ + char *sigc_spbuf[__SUNOS_MAXWIN]; + + /* Windows to restore after signal */ + struct { + unsigned long locals[8]; + unsigned long ins[8]; + } sigc_wbuf[__SUNOS_MAXWIN]; +}; + +typedef struct { + struct { + unsigned long psr; + unsigned long pc; + unsigned long npc; + unsigned long y; + unsigned long u_regs[16]; /* globals and ins */ + } si_regs; + int si_mask; +} __siginfo_t; + +typedef struct { + unsigned long si_float_regs [32]; + unsigned long si_fsr; + unsigned long si_fpqdepth; + struct { + unsigned long *insn_addr; + unsigned long insn; + } si_fpqueue [16]; +} __siginfo_fpu_t; + |